Tag Archives: roadmaps

Jira Roadmaps connect to Confluence, await Code Barrel

Atlassian’s Jira Roadmaps began to sync up with the rest of its cloud-based product line this week, and more integrations will become available this quarter, as users await further streamlining of the company’s tools.

Jira Roadmaps, which offer high-level views into team projects and their projected delivery timelines, became available for the latest version of Jira Software Cloud in October 2018. Jira Software Cloud is distinct from Jira Server, a much older on-premises version of the nearly 20-year-old product.

This week’s updates include several refinements to the Roadmaps workflow interface, such as clearer visualizations of dependencies between Roadmap projects, and finer-grained workflow editing features in the top-level UI. Most significantly, users can now add multiple live Jira Roadmaps images to Confluence documents that offer business managers an organization-wide view of software projects, a key component of enterprise BizDevOps strategy.

“We use Confluence for our internal wiki,” said Chester Dean, director of business technology operations at Looker, a business intelligence firm in Santa Cruz, Calif. “The new integration will give us access to embedded visualizations of next-gen workflows.”

Looker, which Google acquired in June 2019, uses its own project-tracking tools within the previous version of Jira, known as Jira classic, which Atlassian also offers to customers through a partnership between the two companies. Looker still uses the older version of Jira along with the latest version, dubbed Jira next-gen, as users can get started quickly on projects in the newer edition, but the company still relies on some older features.

“We get people to model what they want in next-gen, then build it in classic,” he said. “Next-gen reduces the amount of admin time it takes to learn and understand how to use Jira, but it isn’t yet ready to replace classic for us.”

Jira Roadmaps in Confluence
Atlassian’s Jira Roadmaps can now be embedded in Confluence documents

Jira Roadmaps, Code Barrel offer ease of use

One feature the latest version of Jira lacks is the ability to link workflows between different projects, but an Atlassian spokesperson said that feature is in the works. Dean said he understands that the priority for Atlassian is to keep Jira Roadmaps and the latest version of Jira Software Cloud current.

“There are a bunch of [vendors] building project management tools, and Atlassian has to be there for the next generation of developers,” he said.

Next month, Atlassian will also roll out integration between the latest version of Jira and the Jira automation tools it acquired with Code Barrel last fall. Code Barrel’s rules builder software automates routine tasks for Jira administrators, such as automatically pre-populating issues with associated subtasks.

Non-technical teams at Looker such as marketing and customer service have taken to the latest version of Jira because of such usability features, Dean said.

Still, Dean isn’t alone in wanting more cohesion between the two versions of Jira Software Cloud, as well as between the multiple products in the overall Jira line. Jira Roadmaps for the older version of the product are not yet generally available, but were previewed at the Atlassian Open summit in Boston last October, and users at that event also said they’d like to share information more easily between the two versions of the product.

However, Jira Roadmaps workflows are fundamentally designed to be independent from one another, so that Jira administrators don’t have to manage changes. This may complicate upgrades for users of the older version, but in the long run, analysts warn that enterprises should expect such disruptions.

“From one generation to another, there are new ways of working,” said Thomas Murphy, an analyst at Gartner. “Customers are used to a certain way of doing things, but those features might operate differently than they expect in a new product.”

Atlassian’s software integration balancing act

While cloud-only users wish for more features in common between Jira next-gen and classic, enterprise companies in on-premises and hybrid cloud environments would also like to see some next-gen Jira features added to Atlassian’s Jira Server.

But the company has made clear that its emphasis will be on cloud and next-gen products, and it says more than half of its enterprise customers have already moved to the cloud version. Some 45% of Jira users have also moved to next-gen as of this month, the company said. At this point, Jira Software Cloud and Server products are developed separately on different codebases, which introduce different constraints, making it unlikely they will share features.

In part, this is because Atlassian increasingly competes with Agile planning and DevOps software vendors that don’t offer on-premises products at all, such as Zendesk and GitLab, Gartner’s Murphy said. Another competitive product, Microsoft’s Azure DevOps, offers the same features both on-premises and in the cloud, but Azure DevOps users face their own integration and upgrade challenges as Microsoft moves toward GitHub.

Meanwhile, Atlassian sweetened the cloud deal for reluctant enterprise users when it shored up its cloud security features and began offering a cloud SLA last year, after a move to AWS in 2018 improved its reliability. In November 2019, the company introduced Atlassian Forge, a framework software partners and IT pros can use to convert popular plugins available for on-premises products for use with the cloud suite, which had been another major hindrance to enterprise cloud migration.

Atlassian has pledged to streamline and rationalize all of its Jira products, which include Portfolio for Jira and Jira Align, based on Atlassian’s acquisition of AgileCraft in 2019, and link them through a unified data repository. Company spokespeople said this week that work will continue throughout 2020, along with CI/CD pipeline integration for Jira, likely to be launched at Atlassian Summit in early April.

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NAND flash manufacturers showcase new technologies

NAND flash manufacturers laid out their roadmaps for next-generation products and architectures at the 2018 Flash Memory Summit this month.

As expected, Intel, Micron, SK Hynix and Toshiba talked up 3D NAND flash chips that can store four bits of data per cell, known as quadruple-level cell (QLC). They also spotlighted their 96-layer 3D NAND and outlined roadmaps that extend to 128 layers and beyond to further boost density.

NAND flash manufacturers introduced new efforts to speed performance, raise density and lower costs. Toshiba launched a low-latency option called XL-Flash. Chinese startup Yangtze Memory Technologies Co. (YMTC) hopes to catch up to the flash chip incumbents with its “Xtacking” architecture that can potentially increase performance and bit density. And South Korea-based chipmaker SK Hynix harbors similar aspirations with its so-called “4D NAND” flash that industry experts say is a misnomer.

Key NAND flash manufacturer Samsung was notably absent from the Flash Memory Summit keynotes, a year after discussing its Z-NAND technology at the conference. Z-NAND is another attempt to reduce costs by shifting periphery logic to a place that doesn’t take up space on the flash chip, said Jim Handy, general director and semiconductor analyst at Objective Analysis.

Here are some of the new technologies that NAND flash manufacturers showcased at last week’s Flash Memory Summit:

Toshiba’s XL-Flash

Toshiba’s XL-Flash is based on the company’s single-level cell (SLC) 3D NAND bit column stacked (BiCS) technology and enables optimization for multi-level cell (MLC) flash. The XL stands for excellent latency, according to Shigeo (Jeff) Ohshima, a technology executive in SSD application engineering at Toshiba Memory Corporation.

Ohshima said XL-Flash requires no additional process and is fully compatible with conventional flash in terms of the command protocol and interface. The read latency of XL-Flash could be 10 times faster than conventional TLC flash devices, according to Ohshima.

He said the company has “a lot of room” to do more with its current 3D NAND BiCS flash technology before new nonvolatile memories such as resistive RAM (ReRAM), magnetoresistive RAM (MRAM), and phase change memory ramp up in volume and become dominant.

“So it ain’t over ’til it’s over,” Ohshima said.

Ohshima said a combination of XL-Flash and denser QLC flash could handle a broad range of application workloads and improve overall system performance over the classic storage architecture of DRAM and HDDs. He noted the performance gap between XL-Flash and QLC flash is considerably smaller than the differential between DRAM and HDDs. And, although XL-Flash is slower than DRAM, it costs less and offers higher capacity.

Industry analysts view Toshiba’s XL-Flash and Samsung’s Z-NAND as a low-latency, flash-based response to 3D XPoint memory technology that Intel and Micron co-developed. Intel last year began shipping 3D XPoint-based SSDs under the brand name Optane, and this year started sampling persistent memory modules that use the 3D XPoint technology. Micron has yet to release products based on 3D XPoint.

David Floyer, CTO and co-founder of Wikibon, said Toshiba’s XL-Flash and Samsung’s Z-NAND will never quite reach the performance of Optane SSDs, but they’ll get “pretty close” and won’t cost anywhere near as much.

Handy expects XL-Flash and Z-NAND to read data at a similar speed to Optane, but he said they “will still be plagued by the extraordinarily slow write cycle that NAND flash is stuck with because of quantum mechanics.”

Startup takes on incumbent NAND flash manufacturers

YMTC hopes to challenge established NAND flash manufacturers with Xtacking. YMTC claims the new architecture can improve efficiency and I/O speed, reduce die size and increase bit density, and shorten development time.

“It really takes courage to go down that path because we know that it’s not easy to make that technology work,” YMTC CEO Simon Yang said.

Unlike conventional NAND, Xtacking separates the processing between the flash cell array and the periphery circuitry, or logic, onto different wafers. The startup claimed the high-voltage transistors that conventional NAND typically uses for the periphery circuit limit NAND I/O speed. YMTC claims Xtacking permits the use of lower voltage transistors that can enable higher I/O and more advanced functions, according to YMTC.

“We really can match the DDR4 I/O speed without any limitation,” Yang said.

Yang said results have been encouraging. He said the flash chip yield is increasing, and the reliability of the memory bits through cycling looks positive. YMTC plans to introduce samples of the new Xtacking-based flash technology into the market early next year, Yang said.

“Hopefully, we can catch up with our friends and contribute to this industry,” Yang said.

YMTC started 3D NAND development in 2014 with a nine-layer test chip and later co-developed a 32-layer test chip with Spansion, which merged with Cypress Semiconductor. YMTC moved the chip into production late last year, but Yang said the company held back on volume ramp-up because the first-generation product was not cost competitive.

“We are very much profit-driven,” Yang said. He later added, “We only want to ramp into volume when it’s cost competitive.”

Handy expressed skepticism that YMTC will be able to meet its cost target, but he said YMTC’s Xtacking efforts might help the company to get to market faster.

SK Hynix 4D NAND flash

SK Hynix came up with a new name to describe its latest NAND flash technology. The company said its “4D NAND” puts the periphery circuitry under the charge-trap-flash-based 3D NAND cell array to reduce chip size, cut the number of process steps and lower overall cost over conventional NAND, in which the periphery circuitry is generally alongside the NAND cell.

But, industry analysts say 4D NAND is merely a catchy marketing term and the approach not unique.

“YMTC is stacking a chip on top of the other, whereas Hynix is putting the logic on the same bit but just building it underneath,” Handy said. “The cost of the chip is a function of how big the die is, and if you tuck things underneath other things, you make the die smaller. What Hynix is doing is a good thing, but I wouldn’t call it an innovation because of the fact that it’s the mainstream product for Intel and Micron.”

Intel and Micron have touted their CMOS under the array (CuA) technology in both their 64-layer QLC and 96-layer TLC flash technologies that they claim reduces die sizes and improves performance over competitive approaches. Handy said Samsung has also discussed putting the logic under the flash chip.

Hyun Ahn, senior vice president of NAND development and business strategy at SK Hynix, said his company’s charge-trap-based 4D NAND roadmap starts at 96 layers with a roadmap that extends to 128 layers and beyond using the same platform.

The first SK Hynix 4D NAND technology will begin sampling in the fourth quarter with 96 stacks of NAND cell, I/O speed of 1.2 Gbps per pin, and a mobile package of 11.5 by 12 mm. The chip size is 30% smaller, and 4D NAND can replace two 256 Gb chips with similar performance, according to SK Hynix.

The new SK Hynix 512 Gb triple-level cell (TLC) 4D NAND improves write performance by 30% and read performance by 25% over the company’s prior 72-stack TLC 3D NAND, with 150% greater power efficiency.

Upcoming 1 terabit (Tb) TLC 4D NAND that SK Hynix will sample in the first half of next year fits into a 16 mm by 20 mm ball grid array (BGA) package with a maximum 2 TB for BGA. An enterprise U.2 SSD using the technology will offer up to 64 TB of capacity, according to SK Hynix.

SK Hynix plans to begin sampling 96-stack QLC 4D NAND, with 1 Tb density in a mono die, in the second half of next year. The company said the QLC 4D NAND would provide more than 20% higher wafer capacity than the TLC NAND that it has been producing since the second half of last year. The 72-stack, enterprise-class 3D NAND will represent more than 50% of SK Hynix NAND production this year, the company said.